1. Field of the Invention
The present invention relates to a semiconductor device having a via hole, and a manufacturing method thereof. The invention particularly relates to a semiconductor device having a layout rule, which is that a via hole connecting an upper metallic wiring with a lower metallic wiring extends down along a side of the lower metallic wiring, and a manufacturing method thereof.
2. Discussion of the Background
As a semiconductor device becomes more complex and is scaled down further, a multilayer wiring structure is generally adopted as a wiring technique of the semiconductor device, and it becomes more important to improve the vertical alignment between a wiring and a via hole.
FIG. 8 is schematic sectional view showing an example of a semiconductor device in which the multilayer structure is adopted. In this semiconductor device, as shown in FIG. 8, a field oxide film 2 and a first gate electrode 3 are formed on a silicon (Si) substrate 1. Second gate electrodes 3' are formed on the field oxide film and are used as a wiring. An insulating film 4, typically a silicon oxide film, is formed on the first and the second electrodes 3 and 3', the field oxide film 2, and the entire substrate 1. A metallic wiring 5 of aluminum or another suitable material, which is a lower wiring, is formed on the insulating film 4. A second insulating film 6, typically a silicon oxide film, is formed on the first wiring 5 and the first insulating film 4. A second metallic wiring 8 of aluminum or another suitable material, which is an upper wiring, is formed on the second insulating film 6 in a manner similar to forming the first metallic wiring 5. The second metallic wiring 8 is electrically connected with the first metallic wiring 5 by way of the via hole 7.
However, as seen in FIG. 8, a shift in position of a mask pattern for forming the via hole causes the via hole 7 to extend laterally from the first metallic wiring 5. Therefore, a short or leakage, between the via hole 7 and the gate electrodes 3' or the silicon substrate 1 may be caused.
There is a method shown in FIG. 9 for addressing the above problem. As shown in FIG. 9, side wall spacers 9 of an amorphous silicon and the like, which typically can be etched at a different rate relative to a silicon oxide film used as the second insulating film, are formed at both sides of the metallic wiring 5, and the width of the first metallic wiring is increased substantially. As a result, it becomes less likely that a short will develop between the via hole and the gate electrodes 3' or the silicon substrate 1 disposed under the first metallic wiring 5.
However, when the side wall spacers are formed at the sides of the first metallic wiring, the space between two adjacent first metallic wirings is decreased substantially, and a margin of a step coverage of the second insulating film is decreased. Therefore, it can become more difficult to scale down the semiconductor device. Also, when the side wall spacers are formed, a step for forming a side wall spacer film and a step for etching back are added after forming the first metallic wiring 5. As a result, manufacturing costs of such devices are higher and a yield rate of such devices is decreased.
On the other hand, as seen in FIG. 10, when a material of the second metallic wiring 8 is buried into the via hole 7 using high temperature sputtering or reflow of metal, the via hole 7 is formed in a taper shape of approximately 80 degrees in order to improve a covering rate of the material of the metallic wiring. In this case, the angle .theta. of the taper is usually constant.
When the semiconductor device is scaled down, the size of the via hole is smaller, e.g. 0.5 .mu.m, and the requirements for vertical alignment between the via hole and the first metallic wiring are more stringent. If the angle of the taper is approximately 80 degrees, an area in which the via hole is contacted with the first metallic wiring becomes still smaller. Therefore, a contact resistance between the via hole 7 and the first metallic wiring 5 is increased, and it becomes more difficult to achieve high speed operation of the semiconductor device.
Furthermore, Japanese Laid Open Patent 04-167524 discusses a method for controlling a taper shape of a via hole. In this method, the via hole is etched by a mixture of CHF.sub.3 and CF.sub.4 gas, and a flow rate of the gas is changed continuously as the etching proceeds in order to form the via hole in a taper shape. That is, a ratio of CF.sub.4 is changed from 100 into 10 and then into 50 gradually so that an upper portion of the via hole can be a taper shape and a lower portion of the via hole can be a vertical shape.
However, in this method, as the lower portion of the via hole is formed in a vertical shape, there is concern that the via hole may contact the gate electrode or the silicon substrate. As a result, a short or leakage may occur between the via hole, the gate electrode and/or the silicon substrate. Also, as the upper portion of the via hole is formed in a taper shape, an area in which the via hole contacts with the first metallic wiring decreases, thereby increasing the contact resistance between the metallic wiring and the via hole. Therefore, using the technique discussed in the Japanese patent, can reduce the operational speed of the semiconductor device.